1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit technology and more particularly to memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memory).
2. Description of Prior Art
The efficiency of program operation in flash memory cells is dependent on the coupling ratio between a control gate and a floating gate. In flash memory cells a gate dielectric layer formed over a semiconductor region separates a floating gate from the semiconductor region. Charge is exchanged between the floating gate and the semiconductor region through the gate dielectric layer and the charging and discharging of the floating gate in this way constitute the programming and erasing operations. A control gate is separated from the floating gate by an interlevel dielectric so that the control gate is capacitively coupled to the floating gate and this coupling is utilized to control the voltage dropped across the gate dielectric. Direct exchange of charge between the control gate and floating gate is to be avoided. The coupling ratio is essentially the ratio of the voltage drop across the gate dielectric to the voltage drop across the interlevel dielectric. It is clearly advantageous to have as much of the applied potential as possible across the floating gate to semiconductor region dielectric thereby enhancing the efficiency of the programming and erase operations. Larger coupling ratios are thus more desirable. Since the ratio of the voltage drop across the gate dielectric to the voltage drop across the interlevel dielectric is equal to the inverse of the ratio of the capacitances across these layer it is beneficial to have the control gate-floating gate capacitance as large, and the floating gate-semiconductor region capacitance as small, as is practical. This must take into account that if charge is to pass through the gate dielectric it cannot be too thick and if charge is not to pass through the interlevel dielectric it cannot be too thin. These constraints hinder the setting of the thickness of the dielectric layers to achieve high coupling ratios. In many traditional flash memory cells the areas of the control gate-floating gate capacitor and the floating gate-semiconductor region capacitor are comparable and low coupling ratios are compensated by increased applied voltage. However, increased voltage can give rise to reliability problems. Also, high voltage could require excessive circuitry, which uses valuable cell area and impedes the ability of shrinking the cell.
A traditional floating gate structure in which a higher control gate to floating gate coupling ratio is achieved is shown in FIG. 1. Isolation regions, 6, separate active regions, 4, of a semiconductor region, 2. A floating gate dielectric layer, 8, is formed over the active regions surfaces and conductive floating gates, 10, are disposed over the floating gate dielectric layer. A blanket interlevel dielectric layer, 12, is formed over the floating gates and isolation regions. A conductive layer, 14, over the interlevel dielectric layer forms the control gates and serves as the word lines. The height y, 16, of the floating gates provides additional area for the control gate to floating gate capacitor along the floating gate sidewalls, so this area is made to be larger than the floating gate to semiconductor region capacitor. In standard traditional structures these capacitor areas are comparable. As a result of the increased control gate to floating gate capacitor area, the coupling ratio achieved for the structure of FIG. 1 is increased as compared to standard traditional structures. The factor, by which the coupling ratio for the structure of FIG. 1 is increased over that of standard traditional structures, is given by the ratio of the control gate to floating gate capacitor areas. As can be seen from FIG. 1 the area ratio is 1+(2y/x), where y, 16, is the height of the floating gate and x, 18, is the width of the active region.
In the present invention a structure is disclosed in which the coupling ratio is increased by substantially increasing the area of the control gate-floating gate capacitor so that its area is much larger then the area of the floating gate-semiconductor region capacitor. This is accomplished in a method, which is an integral part of the invention, that utilizes a novel application of the spacer etch technique to fabricate a finger-like floating gate. It is an important feature of the invention that the substantial increase in the control gate-floating gate capacitor area is accomplished without any increase in cell size. With a high coupling ratio resulting from the increased area of the control gate-floating gate capacitor the thickness of the dielectric layers can be maintained as they optimally should be, the gate dielectric layer relatively thin and the interlevel dielectric layer relatively thick. In addition, the applied voltage can be low with resulting improved reliability and reduced circuitry.
Hsieh et al. U.S. Pat. No. 6,312,989 disclose a split gate flash with protruding source that contains a spacer control gate. Hsieh et al. U.S. Pat. No. 6,153,494 teach a method to increase the coupling ratio of control gate, or word line, to floating gate by lateral coupling in stacked-gate flash. U.S. Pat. No. 6,034,393 to Sakamoto et al. shows a nonvolatile semiconductor memory device with trench isolation. U.S. Pat. No. 6,140,182 disclose a nonvolatile memory device with raised isolation regions with increased control gate to floating gate coupling ratio.